Description

The IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2018) is the 26th in a series of international conferences sponsored by the International Federation for Information Processing Technical Committee (IFIP TC) 10 Working Group 5, the Institute of Electrical and Electronics Engineers (IEEE) Council on Electronic Design Automation (CEDA) and the IEEE Circuits and Systems Society (CASS), which explore the state-of-the-art in the areas of Very Large Scale Integration (VLSI) and System-on-Chip (SoC) design. VLSI-SoC 2017 is held under the broad theme: “The Internet of Things: SoC Opportunities and Challenges.”

Previous conferences have taken place in Edinburgh, Trondheim, Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier, Darmstadt, Perth, Nice, Atlanta, Rhodes, Florianópolis, Madrid, Hong Kong, Santa Cruz, Istanbul, Playa del Carmen, Daejeon, and Tallinn.The purpose of VLSI-SoC is to provide a forum to exchange ideas and showcase academic as well as industrial research in architectures, circuits, devices, design automation, verification, test, and security, within digital, analog, and mixed-signal systems.

Call for paper

Description

Research topics of interest include, but are not limited to, the following:

  1. Analog, mixed-signal and sensor architectures
  2. Digital architectures: NoC, multi-core, and reconfigurable
  3. CAD: Synthesis and analysis
  4. Prototyping, verification, modeling, and simulation
  5. Circuits and systems for signal processing and communications
  6. Embedded systems: Architecture, design, and software
  7. Low-power and thermal-aware IC design
  8. Emerging semiconductor technologies
  9. Variability, reliability, and test
  10. Hardware security

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Important dates

  • Conference Dates

    08 Oct.

    2018

    TO

    10 Oct.

    2018

  • 20 Apr.

    2018

    Abstract submission deadline

  • 27 Apr.

    2018

    Draft paper submission deadline

  • 22 Jun.

    2018

    Draft paper acceptance notification

  • 13 Jul.

    2018

    Final paper deadline

Contact information

  • Graziano Pravadelli
  • graziano.pravadelli@univr.it

Sponsored By

  • IEEE Circuits and Systems Society
    IEEE Council on Electronic Design Automation

Organized By

  • IFIP WG10.5
    University of Verona