Functional Testing usual flow comprises the SW or FW code loading into device while keeping the device in reset and execution of predefined function after reset out. To perform this task in test program design verification prepares the test in simulation environment and once it is passing delivers evcd files to the test engineer for further translation and pattern preparation. Structural changes (ad hoc DFT) are widely used to support Structural Based Functional Testing (SBFT). We have developed a method which eliminates the need of verification delivery, design changes due to support SBFT loading and execution and opens the way of using any of existing FW routines. The essence of the method is the implementation of part of Device Driver in the Tester environment. The implemented code manages direct FW loading into the chip, FW to SW communication and FW logging. This scheme provides the basis for functional tests on chip as well all necessary chip configurations for Analog and RF testing. It brings System capabilities into the Tester environment including system like debug. This bestows versatility which benefits the rapid Test Program and silicon validation and helps to increase testing coverage. Implementing the part of the Device Driver in the test program paves the way to the System Level Testing on ATE.