2018 IEEE International Test Conference (ITC)

4 / 2018-01-16 00:56:08

A test mechanism for TSV based 3D DRAM

Through Silicon via (TSV); built in self-test (BIST); 3D on-chip memory.

Abstract— Increasing size of embedded memory on the system on-chip (SoC) and multi-core processors remains a challenge; thus, we propose an on-chip 3D memory based on TSV technology in order to solve the challenge of increasing memory area. Hence, employing on-chip 3D memory is led to decrease hardware overhead induced by increasing size of embedded memory on a SoC near to 59.77% without effecting the volume of stored data in memory. On the other hand, memory testability based on 3D technology likewise should be considered due to high sensitivity in TSV link fault; accordingly, we propose the two test mechanisms based on BIST method which able to detect fault types with high accuracy. The hardware overhead caused by adding test circuit in order to 3D DRAM testability is near to 8.4%.