2019 IEEE European Test Symposium (ETS)

3 / 2018-12-11 17:02:05

Pinhole Defect Characterization and Modeling for STT-MRAM Testing

STT-MRAM,Manufacturing Defects,Fault Modeling

Spin-transfer-torque magnetic RAM (STT-MRAM) is an emerging non-volatile memory technology, which is applicable to both stand-alone and embedded applications. STT-MRAM manufacturing process involves not only traditional CMOS process, but also magnetic tunnel junction (MTJ) fabrication and integration which are more vulnerable to manufacturing defects. In this paper, we provide a comprehensive characterization of pinhole defects in MgO barrier of MTJ device for both t = 0 and t > 0. In addition, we propose a pinhole-parameterized Verilog-A pMTJ compact model, which is calibrated and validated by measured silicon data. Based on this model, we perform singlecell static fault analysis with peripheral circuits.