2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)

6 / 2019-01-15 06:48:14

A 380 MS/s 8-Bit Parallel Array SAR ADC in 65nm CMOS Technology

CMOS; parallell array; SAR ADC

A new parallel array (PA) architecture for a successive approximation register (SAR) ADC is presented in this paper. The N bit PA SAR ADC uses an array of N comparators and N-1 DACs. The ADC conversion frequency is equal to the input track/hold sampling frequency and the latency is one conversion period. No control circuitry is needed. This architecture provides an alternative to conventional sequential, synchronous and asynchronous SAR ADC implementations to meet required power/resolution/conversion frequency profiles for a wide range of applications. An 8 bit implementation in 65nm CMOS technology has a sampling rate of 380MS/s, a Nyquist SNDR of 46.1dB, a power consumption of 2.36mW at 1.0V power supply, and a figure of merit of 37.9fJ/conversion step.