359 / 2019-02-24 11:01:32
Program Voltage Generator with Ultra-Low Ripple for 3D NAND Flash in Standard CMOS Process
program voltage generator,low ripple,3D NAND Flash
Final Paper
Cece Huang / Institute of Microelectronics of Chinese Academy of Sciences
Fei Liu / Institute of Microelectronics of Chinese Academy of Sciences
Qianqian Wang / Institute of Microelectronics of Chinese Academy of Sciences
Chunlong Li / Institute of Microelectronics of Chinese Academy of Sciences
Zongliang Huo / Institute of Microelectronics of Chinese Academy of Sciences
In this paper we present an ultra-low ripple program voltage generator for 3D NAND Flash memories with the scheme of proposed dynamic clock voltage scaling. The noise in program voltage should be minimized to reduce the width of threshold voltage distribution in high density NAND flash. The proposed scheme drastically reduces the output ripple and enhances the system stability. Furthermore, the high voltage regulator occupying large area in conventional generator is not necessary anymore. The generator with an area of 0.55mm2 has been designed in a 0.18µm CMOS process under 1.8V supply voltage. Under the equivalent load condition of 3D NAND Flash, the post-layout simulation results show that the range of output voltage is 15.5V to 23V and the maximum ripple voltage is 1.18mV at 10MHz clock frequency.
Important Date
  • Conference Date

    Jun 12

    2019

    to

    Jun 14

    2019

  • Jun 12 2019

    Draft paper submission deadline

  • Jun 14 2019

    Registration deadline

Organized By
Xi'an University of Technology
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