The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

605 / 2019-03-15 21:42:33

A 112Gb Low-Noise PAM-4 Linear Optical Receiver in 28nm CMOS

28nm CMOS, 112Gb/s, PAM-4, linear optical receiver, low power, low noise, negative capacitance

Plenary track > Analog Circuits

A 112Gb/s PAM-4 linear optical receiver with low noise, high linearity in 28nm CMOS is presented. The receiver signal chain consists of a transimpedance amplifier (TIA), a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. PMOS CML logic is used based on the device characteristics. The low-noise topology and novel gain control techniques together enable state-of-the-art performance. The receiver achieves 2.72μArms input-referred noise current, 71dBΩ transimpedance gain and 37 GHz bandwidth. It is able to provide 18.5dB dynamic range to support maximum input overload current of 1.8mApp. The total harmonica distortion (THD) is below 5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.