Hardware Implementation and comparative evaluation of LIF Neuron Models on FPGA for Neuromorphic Computing
ID:104 View Protection:ATTENDEE Updated Time:2026-07-22 16:10:00 Hits:19 Online

Start Time:2026-07-31 14:55(Asia/Kolkata)

Duration:15min

Session:S6 Artificial Intelligence Use Cases » S6-6Artificial Intelligence Use Cases

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Abstract
Neuromorphic computing is an emerging paradigm for developing energy-efficient artificial intelligence (AI) systems that can perform real-time processing on resource-constrained hardware platforms. The leaky integrate-and-fire (LIF) neuron provides a good balance between biological plausibility and computational simplicity, making it well suited for FPGA-based accelerators. This paper presents a comparative analysis of three neuron architectures: quantized LIF (QLIF), piecewise linear LIF (PWL-LIF) and event-driven refractory LIF (REF-LIF) through FPGA implementation and hardware analysis. The neuron models were assessed in terms of FPGA resource utilization, functional correctness, timing performance, and power consumption. The results show that the QLIF model requires the least hardware resources. REF-LIF provides the best efficiency with measured on-chip power consumption of 0.536 W, and PWL-LIF model provides a balanced trade-off between performance and implementation cost. By comparing the neuron architectures, the study demonstrates the impact of neuron model on FPGA implementation efficiency and practical recommendations for selecting appropriate neuron models for scalable and low-power neuromorphic accelerators in real-time edge AI applications.
Keywords
Neuromorphic computing, Spike neural network (SNN), Artificial neural network(ANN), FPGA, LUT
Speaker
BODOLLA RAHUL YADAV
RESEARCH SCHOLAR J B Institute of Engineering and Technology, Hyderabad, India-500075

Submission Author
BODOLLA RAHUL YADAV J B Institute of Engineering and Technology, Hyderabad, India-500075
M. JAHNAVI LAKSHMI J B Institute of Engineering and Technology, Hyderabad, India-500075
RALLAPALLI S VINITHA J B Institute of Engineering and Technology, Hyderabad, India-500075
D. NARESH J B Institute of Engineering and Technology, Hyderabad, India-500075
K.V.V. SATYA SAI J B Institute of Engineering and Technology, Hyderabad, India-500075
KIRAN PAKMODE J B Institute of Engineering and Technology, Hyderabad, India-500075
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Important Date
  • Conference Date

    Jul 30

    2026

    to

    Aug 01

    2026

  • Jul 28 2026

    Registration deadline

  • Jul 30 2026

    Draft paper submission deadline

Sponsored By
The United Societies of Science
Organized By
Kongunadu College of Engineering and Technology
Supported By
IEEE Section
IEEE Madras Section
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