A Noise-Aware Hybrid Quantum-Classical Framework for Reliable Quantum Information Processing
ID:41 View Protection:ATTENDEE Updated Time:2026-10-04 23:23:31 Hits:95 Online

Start Time:2026-10-12 17:00(Asia/Ho_Chi_Minh)

Duration:15min

Session:S5 Track 5: Emerging Trends of AI/ML » S5-5Track 5: Emerging Trends of AI/ML

Presentation File

Tips: Only the registered participant can access the file. Please sign in first.

Abstract
Quantum‍‌‍‍‌ information technologies have been evolving across computing, communication, sensing, and security. However, the quantum state still suffers from gate errors, measurement errors, decoherence, and other limitations of the hardware. This paper introduces an environment of a noise-aware hybrid quantum-classical for investigating the quantum information processing reliability when the system is under representative noises. The framework is implemented by using quantum circuit execution together with classical circuit analysis, measurement processing, and lightweight error mitigation. Parameterized quantum circuits with different depths are used to illustrate the three types of execution conditions: ideal, noisy, and noise-mitigated. To assess the performance, the following metrics are considered: circuit fidelity, output error, successful-state probability, and execution overhead. As an example, if the circuit fidelity for the ideal case is about 99.8%, it decreases to approximately 86.7% once we consider the noisy situation. On the contrary, our proposed mitigation method helps to enhance that to 93.8%. Apart from showing the effect of circuit depth, the research also considers measurement correction. One of the key results is that practical quantum applications must take into account the interplay between circuit design, hardware noise, and classical processing rather than looking at the quantum algorithm in isolation.
 
Keywords
Quantum Error Correction,Quantum Communication,Quantum Computing
Speaker
Amulya Gurijala
Senior AI/ML Enginee Citizens bank

Submission Author
Amulya Gurijala Citizens bank
Sai Divya Kancharla Hilton grand Vacations
Sangeeth Kumar Vanam TCS
Hari Naga Saran Kumpatla Bank of new york Mellon
Phani Monogya Katikireddi Citizens bank
Submit Comment
Verify Code Change Another
All Comments
Important Date
  • Conference Date

    Oct 11

    2026

    to

    Oct 14

    2026

  • Dec 30 2025

    Contribution Submission Deadline

  • Sep 28 2026

    Early Bird Registration

  • Oct 14 2026

    Draft paper submission deadline

  • Oct 15 2026

    Registration deadline

Sponsored By
United Societies of Science
Organized By
Posts and Telecommunications Institute of Technology
Supported By
IEEE Section
IEEE Vietnam Section