59 / 2015-10-29 13:07:12
10 Gigabit Ethernet TCP frame data registration algorithm based on FPGA
3632,8118,8147,8148
Draft Accepted
夏杨 / Beijing Institute of Technology
越洋 陈 / Beijing Institute of Technology
Using FPGA to achieve full hardware protocol stack in 10 Gigabit Ethernet(10GigE) has the following advantages, such as low cost, wide range of application, high efficiency, etc. Compared with gigabit Ethernet, 10GigE adopts wider data width, which makes hardware face the difficulty of data registration for handling intra-frame data. This paper designed “FIFO form circular-queue handling TCP frame data registration algorithm”, solved the problem of data registration when FPGA device receives, stores and sends TCP frame data and adopted FPGA to build practical system to realize TCP through hard core coding. At the same time, this algorithm can also be used for the data registration of other protocol in 10GigE environments.
Important Date
  • Conference Date

    May 21

    2016

    to

    May 22

    2016

  • Oct 30 2015

    Early Bird Registration

  • Mar 21 2016

    Draft paper submission deadline

  • Apr 01 2016

    Draft Paper Acceptance Notification

  • Apr 10 2016

    Final Paper Deadline

  • May 22 2016

    Registration deadline

Sponsored By
亚利桑那州立大学
查尔斯特大学
重庆环球联合科学技术研究院
韦洛尔理工大学
阿尔托大学
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