Introduction
The goal of achieving exascale performance under stringent power budget is important, exciting, and challenging. One of the biggest impediments in achieving this goal is the excessive data movement across different levels of the memory hierarchy. In this workshop, we intend to discuss innovative ways to reduce this data movement in a variety of architectures (including CPUs, GPUs, handhelds, data centers, IoT, accelerators etc.). We welcome all novel submissions that describe hardware, software, or hardware-software co-design techniques to reduce the data movement.
Call for paper
Submission Topics
Any idea/technique that can help in reducing the data movement is appropriate for this workshop. Some topics (but not limited to) are:
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Near Data Processing (e.g., near caches or memory or storage devices)
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In-Memory Computing (e.g., in caches or memory or storage devices)
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Approximate Computing (e.g., load value approximations)
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Cache/DRAM Locality Optimizations
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Data Compression Techniques
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Emerging Memory Technologies (e.g., STT-RAM, Memristor)
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Non Von-Neumann Architectures (e.g., Quantum Architectures, Automata Processor)
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Interconnection Architectures (e.g., on-chip, off-chip, Ethernet, interposer system, flexible interconnects for FPGA)
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Programming and Language Support for Minimizing Data Movement
All Comments
Important Date
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Sep 09
2017
Conference Date
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Sep 09 2017
Registration deadline
Contact Information
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