First Workshop on RISC-V for Computer Architecture Research (CARRV)

The topics of specific interest for the workshop include, but are not limited to:

• RISC-V simulation/emulation infrastructures, including ports of existing infrastructures

• Easily modifiable RISC-V RTL cores to support research

• Whole-SoC simulators/emulators and/or models built around RISC-V

• RISC-V-based research prototypes

• Machine-readable formal models and verification methodologies

• Compiler toolchains and operating system ports to support systems research

• Security architecture research

• Memory model research

• Quantitative comparison of RISC-V with other ISAs