Introduction

Forum on specification & Design Languages (FDL) is a well established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modelling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. Modelling and specification concepts push the development of new design and verification methodologies to ESL (Electronic System Level) thus providing a means for model-driven and automated design of complex electronic systems in a variety of application domains. FDL gives an opportunity to gain up-to-date knowledge in many broad areas of the fast evolving field of system design and verification.

Call for paper

Important date

2018-04-21
Abstract submission deadline
2018-04-28
Draft paper submission deadline
2018-06-26
Draft paper acceptance notification
2018-07-21
Final paper submission deadline
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Important Date
  • Conference Date

    Sep 10

    2018

    to

    Sep 12

    2018

  • Apr 21 2018

    Abstract Submission Deadline

  • Apr 28 2018

    Draft paper submission deadline

  • Jun 26 2018

    Draft Paper Acceptance Notification

  • Jul 21 2018

    Final Paper Deadline

  • Sep 12 2018

    Registration deadline

Organized By
University of Verona
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