FPT, which was started in 2002, is the premier conference on Field-Programmable Technology in the Asia-Pacific region following the success of FPL (1991-current), FPGA (1992-current), and FCCM (1992-current). FPT2018 is the seventeenth in the series, and the fourth held in Japan. Each FPT has a high-quality discussion with 200 or more experts, and there are about 80 presentations, and the acceptance rate is lower than 30 percents.

Corporate support is typically used to permit a higher number of students to attend FPT at discount registration fees. Exhibits by supporters also help inform researchers – especially students and postdocs – about relevant applications and opportunities. Corporate support can be targeted to a particular event or activity at the Conference.


  • Authors registration:by October 6 October 15, 2018
  • Final-copy of PhD/Demo/Contest papers due: October 15, 2018
  • Final-copy of regular/poster papers due: October 15, 2018
  • Early registration due: October 31, 2018
  • Late registration due: November 25, 2018
  • Workshops, tutorials: December 10-14, 2018
  • FPT'18 Conference: December 12-14, 2018

Call for paper

Important Dates

Draft paper submission deadline:2018-07-30

Call for paper description

FPT is the premier conference in the Asia-Pacific region on field-programmable technologies including reconfigurable computing devices and systems containing such components. Field-programmable devices promise the flexibility of software with the performance of hardware. The development and application of field-programmable technology have become important topics of research and development. Field-programmable technology is widely applied, in high-performance computing systems, embedded and low-power control instruments, mobile communications, rapid prototyping and product emulation, among other areas.

Topics of submission

Submissions are solicited on new research results and detailed tutorial expositions related to field-programmable technologies, including but not limited to:

  • Tools and Design techniques for field-programmable technology including placement, routing, synthesis, verification, debugging, runtime support, technology mapping, partitioning, parallelization, timing optimization, design and run-time environments, high-level synthesis (HLS) compilers, languages and modeling techniques, provably-correct development, intellectual property core-based design, domain-specific development, hardware/software co-design.
  • Architectures for field-programmable technology including field-programmable gate arrays, complex programmable logic devices, coarse-grained reconfigurable arrays, field-programmable interconnect, field-programmable analogue arrays, field-programmable arithmetic arrays, memory architectures, interface technologies, low-power techniques, adaptive devices, reconfigurable computing systems, high-performance reconfigurable systems, evolvable hardware and adaptive computing, fault tolerance and avoidance.
  • Device technology for field-programmable logic including programmable memories such as non-volatile, dynamic and static memory cells and arrays, interconnect devices, circuits and switches, and emerging VLSI device technologies.
  • Applications of field-programmable technology including accelerators for biomedical/scientific/neuro-morphic computing and machine learning, network processors, real-time systems, rapid prototyping, hardware emulation, digital signal processing, interactive multimedia, machine vision, computer graphics, cryptography, robotics, manufacturing systems, embedded applications, evolvable and biologically-inspired hardware.
  • Education for field-programmable technology including courses, teaching and training experience, experiment equipment, design and applications.


Leave a message


Contact information


Sponsored By

  • IEEE Electron Devices Society
    IEEE Tokyo/Japan Sections Jt CEDA Chapter