AMSER-FF: Area-Minimized Soft-Error-Recoverable Flip-Flop for Radiation Hardening
ID:72 View Protection:ATTENDEE Updated Time:2021-08-23 14:23:03 Hits:721 Oral Presentation

Start Time:2021-08-20 22:05(Asia/Shanghai)

Duration:20min

Session:SS Special Session » SS4A6. Test Methods Towards Zero Failure Rate for Safety-Critical ICs

Video No Permission Presentation File Attachment File

Tips: Only the registered participant can access the file. Please sign in first.

Abstract
Among various radiation hardening by designs (RHBD), triple-modular redundancy (TMR) is
frequently used to correct soft errors. One of the wellknown TMR solutions is called ∆TMR, which makes
three copies of flop-flops (FFs) and inserts different delay buffers in front of data inputs of the second
and third FFs for capturing soft errors. However, such solution has shortcomings in the area/power overhead
and the imbalanced rise/fall delay. As a result, a novel TMR flip-flop design called area-minimized soft-errorrecoverable flip-flop (AMSER-FF) is proposed in this paper to reduce the area/power overhead and timing degradation. Each AMSER-FF embeds a reference voltage generator (RVG), which generates balanced rise/fall delay and has fixed area utilization instead
of inserting delay buffers for correcting errors. Experimental results show that AMSER-FF achieves lower
area overhead, power overhead and less timing degradation than ∆TMR.
 
Keywords
Speaker
Charles H.-P. Wen
Professor National Yang Ming Chiao Tung University

Prof. Hung-Pin (Charles) Wen received the Ph.D. degree in very large-scale integration (VLSI) verification and test from the University of California at Santa Barbara, Santa Barbara, CA, USA, in 2007. He is currently a Distinguished Professor (2020-now) with National Yang Ming Chiao Tung University, Hsinchu, Taiwan, where he is also a specialist in computer engineering. Over the past few years, his research has been focused on applying machine learning and data mining to system-on-chip designs (including radiation hardening, functional verification, and timing analysis) and cloud networking (especially on performance analysis and architecture design of large-scale data centers). Prof. Wen was a recipient of the Best Paper Awards from the 2012 Asia and South Pacific Design Automation Conference (ASP-DAC), the 2014 Synthesis And System Integration of Mixed Information (SASIMI), the 2016 International Conference on Information Networking (ICOIN), the 2017 ICOIN, and the Distinguished Young Scholar Award of the Taiwan IC Design Society.
 

Submit Comment
Verify Code Change Another
All Comments
Important Date
  • Conference Date

    Aug 18

    2021

    to

    Aug 20

    2021

  • May 10 2021

    Draft paper submission deadline

  • Aug 16 2021

    Early Bird Registration

  • Aug 19 2021

    Contribution Submission Deadline

  • Aug 20 2021

    Registration deadline

Sponsored By
IEEE
Tongji University
Chinese Computer Federation
Organized By
Tongji University
Previous Conferences