Presentation List

Characterization, Modeling and Test of SyntheticAnti-FerromagnetFlip Defect in STT-MRAMs

Lizhou Wu Post Doc. Delft University of Technology

SS /SS5 2021-08-20 21:05 ~ 21:25

PUBLIC Invited speech

Fault Modeling and Testing of Spiking Neural Network Chips

I-Wei Chiu National Taiwan University；Li James Chien Mo National Taiwan University

RS /RS1 2021-08-19 20:40 ~ 21:00

PUBLIC Oral Presentation

A N:1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs

Danqing Li HeFei University of Technology

SS /SS1 2021-08-19 20:40 ~ 21:00

PRIVATE Oral Presentation

Scalable Parallel Static Learning

Xiaoze Lin student Shantou University

SS /SS2 2021-08-19 22:10 ~ 22:30

ATTENDEE Oral Presentation

Learning A Wafer Feature with One Training Sample

Yueling Jenny Zeng University of California Santa Barbara

SS /SS5 2021-08-20 22:05 ~ 22:25

ATTENDEE Oral Presentation

Industrial Application of IJTAG Standards to the Test of Big-A/little-d Devices – plus Updates to the Latest State of IEEE P1687.2

Hans Martin von Staudt DIALOG SEMICONDUCTOR

SS /SS5 2021-08-20 21:25 ~ 22:05

ATTENDEE Oral Presentation

Designing Parallel TAMs for 3D-SICs Based on IEEE Std 1838’s Flexible Parallel Port Leveraging Lessons-Learned on 2D-SOCs

Erik Jan Marinissen Scientific Director imec

SS /SS3 2021-08-20 20:40 ~ 21:00

PUBLIC Oral Presentation

Testing and Fault-Localization Solutions for Monolithic 3D ICs

Arjun Chaudhuri Duke University

SS /SS3 2021-08-20 20:20 ~ 20:40

ATTENDEE Oral Presentation

3D Test Wrapper Design and Physical Optimization

Vivek Chickermane Cadence Design Systems；Subhasish Mukherjee Cadence

SS /SS3 2021-08-20 20:00 ~ 20:20

ATTENDEE Oral Presentation

An optimized DFT technology based on machine learning

Han Yang Nanjing University of Posts and Telecommunications

SS /SS2 2021-08-19 22:30 ~ 22:50

ATTENDEE Oral Presentation

2021 IEEE International Test Conference in Asia (ITC-Asia 2021)

Characterization, Modeling and Test of SyntheticAnti-FerromagnetFlip Defect in STT-MRAMs

Fault Modeling and Testing of Spiking Neural Network Chips

A N:1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs

Scalable Parallel Static Learning

Learning A Wafer Feature with One Training Sample

Industrial Application of IJTAG Standards to the Test of Big-A/little-d Devices – plus Updates to the Latest State of IEEE P1687.2

Designing Parallel TAMs for 3D-SICs Based on IEEE Std 1838’s Flexible Parallel Port Leveraging Lessons-Learned on 2D-SOCs

Testing and Fault-Localization Solutions for Monolithic 3D ICs

3D Test Wrapper Design and Physical Optimization

An optimized DFT technology based on machine learning

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