Description

As we look beyond the petascale era, accelerators such as Graphics Processing Units (GPUs) and FPGAs, as well as upcoming integrated hybrid processing cores, are expected to play a preeminent role in architecting the largest systems in the world. While there is significant interest in these architectures, much of this interest is an artifact of the hype associated with them. This workshop focuses on understanding the implications of accelerators on the architectures and programming environments of future systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance or productivity of applications trying to use these systems. The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other hybrid systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.

Call for paper

Topics of submission

We are soliciting contributions in areas including but not limited to: Characterizing strategies for implementing and optimizing HPC applications for accelerators. Techniques for optimizing kernels for execution on GPUs and future hybrid platforms. Model

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Contact information

  • ashes13-chairs@mcs.anl.gov

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