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Recent years have seen a significant rise in the number of cores that can be integrated in the same chip multiprocessor. However, before this trend translates into effective parallel performance improvement, the research community has to address several underlying challenges. Providing efficient and scalable inter-core and core-to-memory communication is regarded as one of the most important challenges since communication is becoming the main performance, power and area constraints of many-core designs. On the one hand, research in Network-on-chip (NoC) and emerging interconnect technologies is showing outstanding results towards alleviating such issue. On the other hand, a less explored research avenue, addressed in this workshop, is to design and develop many-core architectures that will take advantage of the unique communication capabilities that these new interconnect fabrics could offer, potentially leading to highly scalable multicore computers.
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This workshop aims to capture the state-of-the-art, engage the community and prospect a long-term vision of this field, which bridges the disciplines of computer architecture and on-chip communication networks, by soliciting original and novel cutting-edg
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  • Conference Date

    Jun 23



    Jun 27


  • Jun 27 2013

    Registration deadline

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