Introduction
Present and future multi-core architectures pose a variety of challenges for system developers: non-cache-coherent memory, heterogeneous processing cores and the exploitation of novel architectural features, such as systems-on-chip (SoCs), distributed switching fabrics, silicon photonics, and programmable hardware. In the near future, we expect to see "rack-scale computers" with 1,000s of cores and terabytes of memory, connected with bandwidth and latency comparable to today's smaller-scale NUMA servers.
MaRS ’16 is a forum for researchers in the hardware, networking, storage, operating systems, language runtime and virtual machine communities to present their experiences with and discuss innovative designs and implementations for these new architectures.
Call for paper
Submission Topics
Topics of interest include, but are not limited to:
- novel multi-core and rack-scale operating system designs,
- System-on-chip (SoC) and Network-on-chip (NoC) designs,
- runtime systems and programming environments for future hardware,
- low-latency and optical networking,
- OS or runtime support for heterogeneous processing cores,
- non-cache-coherent shared memory,
- scheduling on many-core and rack-scale architectures,
- programmable hardware,
- energy efficiency, fault tolerance and resource management on future multi-core and rack-scale architectures,
- rack-scale storage,
- performance evaluation of emerging hardware,
- architectural support for systems-level software,
- case studies of system-level software design for current or future multi-core and rack-scale hardware, and
- applications for and experiences with multi-core and rack-scale systems
All Comments
Important Date
-
Apr 18
2016
Conference Date
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Apr 18 2016
Registration deadline
Contact Information
- Boris Grot
- bo******@ed.ac.uk
- +44*********
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