Welcome to Austin for the 35th edition of the IEEE/ACM International Conference on Computer-Aided Design. As a premier conference co-sponsored by IEEE and ACM, the technical program of ICCAD covers wide research areas including design automation, system level design, embedded systems, and hardware security. For 2016, we are back in Austin, at the heart of beautiful Texas Hill Country, the live music capital of the world and a vibrant hub of technology innovations. The Executive Committee is in the process of putting together an engaging program. We look forward to seeing you in November.

Call for paper

Topics of submission


1.1 System Design

  • System-level specification, modeling, and simulation

  • System design flows and methods

  • HW/SW co-design, co-simulation, co-optimization, and co-exploration

  • HW/SW platforms for rapid prototyping

  • System design case studies and applications

  • System-level issues for 3D integration

  • Micro-architectural transformation

  • Memory architecture and system synthesis

  • System communication architecture

  • Network-on-chip design methodologies and CAD

  • Network-on-chip design case studies and prototyping

1.2 Hardware for Embedded Systems

  • Multi-core/multi-processors systems

  • HW/SW co-design for embedded systems

  • Static and dynamic reconfigurable architectures

  • Memory hierarchies and management

  • System-level consideration of custom storage architectures (flash, phase change memory, STT-RAM, etc.)

  • Application-specific instruction-set processors (ASIPs)

1.3 Embedded System Software

  • Real-time software and operating systems

  • Middleware and virtual machines

  • Timing analysis and WCET

  • Programming models for multi-core systems

  • Profiling and compilation techniques

  • Design exploration, synthesis, validation, verification, and optimization

1.4 System-level Security

  • Hardware-based security (CAD for PUF’s, RNG, AES etc)

  • Detection and prevention of hardware Trojans

  • Side-channel attacks, fault attacks and countermeasures

  • Split Manufacturing for security

  • System software security techniques

  • Design for security

  • CAD for security

  • Security implications of CAD

  • Cyberphysical system security

  • Nanoelectronic security

  • Counterfeiting

  • Supply chain security

1.5 Dark Silicon and Power/Thermal Considerations in System Design

  • Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems

  • Energy- and thermal aware application mapping and scheduling

  • Energy- and thermal-aware dark silicon system design and optimization

  • Run-time management for the dark silicon

1.6 Design Issues for Heterogeneous Computing & Cloud Computing

  • Hardware-software partitioning of workloads

  • Modeling and simulation of heterogeneous platforms

  • High-level synthesis for heterogeneous computing

  • Power/performance analysis of heterogeneous and cloud platforms

  • Programming environment of heterogeneous computing

  • Acceleration techniques including GPGPU and FPGA and dedicated ASIC’s

  • Application driven heterogeneous platforms for big data, machine learning etc.

  • Cloud Internet-of-Things (IoT) applications

  • Interaction of Internet-of-Things (IoT) devices and the cloud

  • Cloud computation for Internet-of-Things (IoT) devices


2.1 High-level, Behavioral, and Logig Synthesis and Optimization:

  • High-level/Behavioral/Logic synthesis

  • Technology-independent optimization and technology mapping

  • Functional and logic timing ECO

  • Resource scheduling, allocation, and synthesis

  • Interaction between logic synthesis and physical design

2.2 Validation, Simulation, and Verification

  • High-level/Behavioral/Logic modeling and validation

  • High-level/Behavioral/Logic simulation

  • Formal, semi-formal, and assertion-based verification

  • Equivalence and property checking

  • Emulation and hardware simulation/acceleration

  • Post-silicon functional validation

2.3 Cell-Library Design, Partitioning, Floorplanning, Placement

  • Cell-library design and optimization

  • Transistor, gate, and wiring sizing

  • High-level physical design and synthesis

  • Estimation and hierarchy management

  • 2D and 3D partitioning, floorplanning, and placement

  • Post-placement optimization

  • Buffer insertion and interconnect planning

2.4 Clock Network Synthesis, Routing, and Post-Layout Optimization and Verification

  • 2D and 3D clock network synthesis

  • 2D and 3D global and detailed routing

  • Package-/Board-level routing and chip-package-board co-design

  • Post-layout/-silicon optimization


3.1 Design for Manufacturability

  • Process technology characterization, extraction, and modeling

  • CAD for design/manufacturing interfaces

  • CAD for reticle enhancement and lithography-related design

  • Variability analysis and statistical design and optimization

  • Yield estimation and design for yield

  • Physical verification and design rule checking

3.2 Design for Reliability

  • Analysis and optimization for device-level reliability issues (stress, aging effects, ESD, etc.)

  • Analysis for interconnect reliability issues (electromigration, thermal, etc)

  • Reliability issues related to soft errors

  • Design for resilience and robustness

3.3 Testing

  • Digital fault modeling and simulation

  • Delay, current-based, low-power test

  • ATPG, BIST, DFT, and compression

  • Memory test and repair

  • Core, board, system, and 3D IC test

  • Post-silicon validation and debug

  • Analog, mixed-signal, and RF test

3.4 Timing, Power Networks, and Signal Integrity

  • Deterministic and statistical static timing analysis and optimization

  • Power and leakage analysis and optimization

  • Circuit and interconnect-level low power design issues

  • Power/ground network analysis and synthesis

  • Signal integrity analysis and optimization

3.5 CAD for RF/Analog and Multi-Domain Modeling and Interconnect

  • CAD for analog, mixed-signal, RF

  • CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electro-optical) devices, circuits, and systems

  • CAD for nanophotonics

  • Device, interconnect and circuit extraction and simulation

  • Package modeling and analysis

  • EM simulation and optimization

  • Behavior modeling of devices and interconnect

  • Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)


4.1 Biological Systems and Electronics, Brain Inspired Computing, and New Computing Paradigms

  • CAD for biological computing systems

  • CAD for systems and synthetic biology

  • CAD for bio-electronic devices, bio-sensors, MEMS, and systems

  • Design methods for learning on a chip

  • Design methodologies for neuromorphic computing

  • Design methods for stochastic and statistical computing

  • Design methods for approximate computing

4.2 Nanoscale and Post-CMOS Systems

  • New device structures and process technologies

  • New memory technologies (flash, phase change memory, STT-RAM, memristor, etc.)

  • Nanotechnologies, nanowires, nanotubes, graphene, etc.

  • Quantum computing

  • Optical devices and communication

  • CAD for bio-inspired and neuromorphic systems

4.3 CAD for Cyber-Physical Systems

  • CAD for Internet-of-Things (IoT) and sensor networks

  • Design issues for Internet-of-Things (IoT) Devices

  • CAD for automotive systems and power electronics

  • Analysis and optimization of data centers

  • CAD for display electronics

  • Green computing (smart grid, energy, solar panels, etc.)


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Important dates

  • Conference Dates

    07 Nov.



    10 Nov.


Contact information

  • Robin Albright
  • 1303-5304562

Sponsored By

  • Association for Computing Machinery Special Interest Group on Design Automation - ACM SIGDA