Introduction
Computing systems with a large number of processing units are increasingly common, both in the form of processors employing multiple execution cores (e.g., multi-core CPUs, GPUs), or computing clusters with a large number of nodes. These many-core architectures bring up new capabilities, opportunities, as well as challenges. As the number of cores increases, so does the probability to have faults, both due to hardware issues (e.g., physical defects introduced during fabrication), software problems (e.g., a single crashed process bringing down the whole computation) or communication issues in the network infrastructure.
This workshop focuses on software and/or hardware solutions to dependability and fault-tolerance in multi- and many-core systems.
Call for paper
Submission Topics
The DMCC Workshop topics of interest include (but are not limited to) the following:
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Dependable/Fault-Tolerant Many-Core Architectures
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Power-Aware Many-Core Design
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Dependable & Secure Many-Core Designs
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Many-Core Development and Design Tools
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Dependability and Fault Tolerance in Simulation
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System-Level Many-Core Implementation
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Many-Core Interconnect Technology
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Many-Core System-On-Chip Development
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Reconfigurable Computing and FPGAs
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Design for Testing
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Hardware and Software Debug Facilities
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Many-Core Programming and Optimization for Dependability
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Application Partitioning and Load Balancing
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Hypervisors and Virtual Machine Technology
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Trusted and Untrusted Environments
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Virtualization for Dependability
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Dependability through Multi-Threading / Multi-Processing
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Fault Detection Techniques
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Fault-Tolerant Software Design
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Fault-Tolerant Hardware Design
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Fault-Tolerant HW/SW Co-Design
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Modeling and Simulation of Dependable and Fault Tolerant Systems
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Formal Techniques for Dependable Hardware/Software Design
All Comments
Important Date
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Conference Date
Jul 18
2016
toJul 22
2016
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Jul 22 2016
Registration deadline
Contact Information
- Thomas Hollstein
- th******@ati.ttu.ee
- 372*********
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