Introduction
The purpose of this workshop is to bring researchers and practitioners of LSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL), high level and system level testing. WRTLT’16, the seventeenth workshop, will be held in conjunction with the 25th Asian Test Symposium (ATS’16) in Hiroshima, Japan. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip (SoC) devices.
Call for paper
Important date
Submission Topics
Areas of interest include but not limited to:
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RTL fault modeling, ATPG, DFT, BIST
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High-level fault modeling, testing and synthesis for testability
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Functional fault modeling and test bench generation
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3D IC testing
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SoC/NoC testing, test scheduling, core-based testing, interconnect testing
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Reliable SoC, system level reliability, self repair, fault tolerant SoC
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Microprocessor testing, design verification
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Important Date
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Conference Date
Nov 24
2016
toNov 25
2016
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Sep 02 2016
Draft paper submission deadline
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Oct 10 2016
Final Paper Deadline
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Nov 25 2016
Registration deadline
Sponsored By
Contact Information
Previous Conferences
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2017-11-30 Taiwan, China
Workshop on RTL and High Level Testing 2017
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