The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest. 

PACT started as a Data Flow Workshop in conjunction with ISCA 1989 but quickly evolved into a unique venue at the intersection of classical parallel architecture and compilers. 

Recently, PACT widened its scope to include insights useful for the design of machines and compilers from applications such as, but not limited to, machine learning, data analytics and computational biology. 

Call for paper

Topics of submission

PACT solicits novel papers, workshops, tutorials, and entries to an ACM student research competition on a broad range of topics that include, but are not limited to:

  • Parallel architectures and computational models

  • Compilers and tools for parallel computer systems

  • Multicore, multithreaded, superscalar, and VLIW architectures

  • Compiler/hardware support for hiding memory latencies

  • Support for correctness in hardware and software

  • Reconfigurable parallel computing

  • Dynamic translation and optimization

  • I/O issues in parallel computing and their relation to applications

  • Parallel programming languages, algorithms and applications

  • Middleware and run time system support for parallel computing

  • Application-specific parallel systems

  • Applications and experimental systems studies of parallel processing

  • Relevant aspects of distributed computing and mobile computing

  • Heterogeneous systems using various types of accelerators

  • Insights from modern parallel applications such as, but not limited to, machine learning, data analytics, and computational biology for the design of parallel architectures and compilers


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Important dates

  • Conference Dates

    09 Sep.



    13 Sep.


  • 14 Mar.


    Draft paper submission deadline

  • 24 May.


    Draft paper acceptance notification

  • 19 Jul.


    Final paper deadline

Contact information

  • Rajeev Balasubramonian

Sponsored By

  • IEEE Computer Society
    Association for Computing Machinery Special Interest Group on Computer Architecture