Introduction

The IEEE International Integrated Reliability Workshop (IIRW) originated from the Wafer Level Reliability Workshop in 1982. The IIRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.
Tutorials, paper presentations, poster sessions, moderated discussion groups, special interest groups, and the informal format of the technical program provide a unique environment for understanding, developing, and sharing reliability technology and test methodologies for present and future semiconductor applications as well as ample opportunity for open discussions and interactions with colleagues.

Hot reliability topics for the workshop include: SiGe and strained Si, III-V, SOI, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, organic electronics, emerging memory technologies (RRAM etc.) and future "nano"-technologies, NEMS/MEMS, photovoltaics, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, product reliability and burn-in strategy, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, single event upsets, as well as the traditional topics of wafer level reliability (WLR) and built-in reliability (BIR).

Call for paper

Important date

2018-07-16
Abstract submission deadline
2018-09-13
Draft paper submission deadline
2018-08-13
Draft paper acceptance notification
2018-10-07
Final paper submission deadline

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics:

  • Designing-in reliability (products, circuits, systems, processes)
  • Resistive memory: degradation mechanisms
  • Deep sub-micron transistor and circuit reliability
  • Customer product reliability requirements / manufacturer reliability tasks
  • Root cause defects, physical mechanisms, and simulations
  • Wafer level reliability tests, test approaches, and reliability test structures
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Important Date
  • Conference Date

    Oct 07

    2018

    to

    Oct 11

    2018

  • Jul 16 2018

    Abstract Submission Deadline

  • Aug 13 2018

    Draft Paper Acceptance Notification

  • Sep 13 2018

    Draft paper submission deadline

  • Oct 07 2018

    Final Paper Deadline

  • Oct 11 2018

    Registration deadline

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