1180 / 2019-07-15 21:16:49
Implementation of Fast Bus Tripping Scheme using Microprocessor-based Relays
Draft Accepted
kris qin / maniotba hydro
Ding Lin / manitoba hydro
Lana Zhu / manitoba hydro
With the introduction of microprocessor-based relays, a low-cost Fast Bus Tripping Scheme can be implemented to provide a fast and selective solution for faults on distribution buses. The scheme consists of microprocessor-based overcurrent relays installed for each feeder and for each main supply. Fast Bus Tripping Scheme is designed to speed up clearing time for a distribution bus fault with a resultant decrease in the arc flash hazard. This paper elaborates a Fast Bus Tripping Scheme design example for three sections of the distribution buses under all operating scenarios, presents key considerations identified during design practice from different perspectives, such as CT connection arrangement, applied protection functionalities, relay time coordination and relay communication methods. Recommendations have been provided accordingly.
Important Date
  • Conference Date

    Oct 21



    Oct 24


  • Oct 13 2019

    Abstract Notification of Acceptance

  • Oct 13 2019

    Draft paper submission deadline

  • Oct 14 2019

    Draft Paper Acceptance Notification

  • Oct 29 2019

    Final Paper Deadline

Organized By
Xi'an Jiaotong University
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