Introduction

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

 

 

Committee

Organizing Committee

General co-Chairs Filomena Decuzzi European Space Agency, The Netherlands filomena.decuzzi@esa.int
Carlo Cazzaniga UKRI-STFC, ChipIr, United Kingdom carlo.cazzaniga@stfc.ac.uk
Program co-Chairs Adrian Evans CEA, France adrian.evans@cea.fr
Jaume Abella Barcelona Supercomputing Center, Spain jaume.abella@bsc.es
Special Session Mario Barbareschi University of Naples, Italy mario.barbareschi@unina.it
Publicity Chair Pedro Reviriego Universidad Politécnica de Madrid, Spain pedro.reviriego@upm.es  
Shanshan Liu University of Electronic Science and Technology of China, China ssliu@uestc.edu.cn
Publication Chair Marcello Traiola INRIA, France marcello.traiola@inria.fr  
Web Chair Bruno Endres Forlin University of Twente, The Netherlands b.endresforlin@utwente.nl
Call for paper

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies, RISC-V architectures and AI-based solutions. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, availability, and security that are affected by defects during manufacturing and by faults during system operation are of interest. Topics include (but are not limited to) the following:

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1. Yield Analysis and Modeling
Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.

2. Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.

3. Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, low power design and micro-processors, including RISC-V architectures

4. Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.

5. Dependability Analysis and Validation
Fault injection techniques and frameworks; dependability and characterization, cross-layer reliability analysis, dependability analysis for AI and machine learning.

6. Repair, Restructuring and Reconfiguration
Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.

7. Defect and Fault Tolerance
Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.

8. Radiation effects
SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.

9. Aging and Lifetime Reliability
Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.

10. Dependable Applications and Case Studies
Methodologies and case studies: 2.5D/3D ICs, IoT, automotive/railway/avionics/space, autonomous systems, industrial control, fail-safe systems, dependable AI.

11. Emerging Technologies
Error management techniques for quantum computing, memristors, spintronics, microfluidics, approximate computing, etc.

12. Design for Security
Fault attacks, fault tolerancebased countermeasures, scan-based attacks and countermeasures, hardware trojans, system obfuscation and logic locking, secure AI, security vs. reliability, interaction between VLSI test, trust, and reliability.

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