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Introduction

The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system, board, and device testing with design, manufacturing and field consideration in mind. 

 

The 33rd IEEE Asian Test Symposium (ATS 2024) is going to be held at Ahmedabad, Gujarat (India), the epicentre of India Semiconductor Mission during December 17-20, 2024.

 

Scope


Original papers on, but not limited to, the following areas are invited:
• Analog/Mixed-Signal Test
• Automatic Test Generation
• Board Test and Diagnosis
• Boundary Scan Test
• Built-In Self-Test (BIST)
• Defect-Based Test
• Delay and Performance Test
• Dependability and Functional Safety
• Design for Test (DFT)
• Diagnosis and Silicon Debug
• Economic of Test
• Failure Analysis
• Fault Modelling and Simulation
• Fault Tolerance
• GPU Test
• High-Speed I/O Test
• Low-Power IC Test
• Memory Test and Repair
• Test for MEMS and Microfluidic Systems
• Multi-/Many-core Processor Test
• Test for Nanoscale Devices and Emerging Technologies
• On-line Test
• Power/Thermal/Reliability Issues in Test
• Reconfigurable System Test
• Test for Biomedical Circuits and Systems
• RF Test
• Hardware-oriented Security and Trust
• Self-Repair
• Test for Sensors and IoT
• SiP, Stacked, 3D IC Test
• Standards in Test
• Machine Learning in Test
• Test Compression
• Test Quality
• Test Synthesis
• Validation and Verification
• Yield Analysis and Enhancement
• Test for Reversible and Quantum Circuits


Regular Sessions: The ATS’24 Program Committee invites original, unpublished paper submissions on the above topics. Paper submissions should be complete manuscripts, not exceeding six pages (including figures, tables, and bibliography) in a standard IEEE two-column format. The submission will be considered evidence that upon acceptance the author(s) will submit a final camera-ready version of the paper or inclusion in the proceedings, and will present the paper at the symposium. ATS reserves the right to remove from IEEE Xplore papers not presented at the symposium. The best paper will be selected by the ATS’24 Program Committee for the best paper award based on the criteria of innovation, potential impact, and presentation quality.



Submission
All submission should be made electronically in PDF format at  https://cmt3.research.microsoft.com/ATS2024/Submission/Index.   A submission should contain a complete manuscript within a limit 6 pages in 10-point single-spaced double-column format, an abstract of 50-200 words. The paper must be submitted for blind review process. Once a submission is accepted, the author(s) must prepare the final camera-ready manuscript in time for being included in the proceedings, and present the paper at the symposium. In case of any difficulty in submission, authors may contact ats2024.nu@nirmauni.ac.in

IMPORTANT DATES:
Paper submission deadline                 : August 15, 2024
Notification of acceptance                  : September 15, 2024
Camera-ready paper due                   : November 15, 2024

Conference:                                       :December 17, 2024                                                                                  

Submission Link: https://cmt3.research.microsoft.com/ATS2024/Submission/Index


The organizing committee of ATS 2024 invites you and your colleagues to submit research articles and attend this prestigious Symposium scheduled to be held at Ahmedabad (India), the epicentre of Indian Semiconductor Mission.

The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system, board, and device testing with design, manufacturing and field consideration in mind. 

 

The 33rd IEEE Asian Test Symposium (ATS 2024) is going to be held at Ahmedabad, Gujarat (India), the epicentre of India Semiconductor Mission during December 17-20, 2024.

 

Scope


Original papers on, but not limited to, the following areas are invited:
• Analog/Mixed-Signal Test
• Automatic Test Generation
• Board Test and Diagnosis
• Boundary Scan Test
• Built-In Self-Test (BIST)
• Defect-Based Test
• Delay and Performance Test
• Dependability and Functional Safety
• Design for Test (DFT)
• Diagnosis and Silicon Debug
• Economic of Test
• Failure Analysis
• Fault Modelling and Simulation
• Fault Tolerance
• GPU Test
• High-Speed I/O Test
• Low-Power IC Test
• Memory Test and Repair
• Test for MEMS and Microfluidic Systems
• Multi-/Many-core Processor Test
• Test for Nanoscale Devices and Emerging Technologies
• On-line Test
• Power/Thermal/Reliability Issues in Test
• Reconfigurable System Test
• Test for Biomedical Circuits and Systems
• RF Test
• Hardware-oriented Security and Trust
• Self-Repair
• Test for Sensors and IoT
• SiP, Stacked, 3D IC Test
• Standards in Test
• Machine Learning in Test
• Test Compression
• Test Quality
• Test Synthesis
• Validation and Verification
• Yield Analysis and Enhancement
• Test for Reversible and Quantum Circuits


Regular Sessions: The ATS’24 Program Committee invites original, unpublished paper submissions on the above topics. Paper submissions should be complete manuscripts, not exceeding six pages (including figures, tables, and bibliography) in a standard IEEE two-column format. The submission will be considered evidence that upon acceptance the author(s) will submit a final camera-ready version of the paper or inclusion in the proceedings, and will present the paper at the symposium. ATS reserves the right to remove from IEEE Xplore papers not presented at the symposium. The best paper will be selected by the ATS’24 Program Committee for the best paper award based on the criteria of innovation, potential impact, and presentation quality.



Submission
All submission should be made electronically in PDF format at  https://cmt3.research.microsoft.com/ATS2024/Submission/Index.   A submission should contain a complete manuscript within a limit 6 pages in 10-point single-spaced double-column format, an abstract of 50-200 words. The paper must be submitted for blind review process. Once a submission is accepted, the author(s) must prepare the final camera-ready manuscript in time for being included in the proceedings, and present the paper at the symposium. In case of any difficulty in submission, authors may contact ats2024.nu@nirmauni.ac.in

IMPORTANT DATES:
Paper submission deadline                 : August 15, 2024
Notification of acceptance                  : September 15, 2024
Camera-ready paper due                   : November 15, 2024

Conference:                                       :December 17, 2024                                                                                  

Submission Link: https://cmt3.research.microsoft.com/ATS2024/Submission/Index


The organizing committee of ATS 2024 invites you and your colleagues to submit research articles and attend this prestigious Symposium scheduled to be held at Ahmedabad (India), the epicentre of Indian Semiconductor Mission.

Committee
Name Affiliation
Advisory Committee
Prof. Adit Singh Auburn University
Prof Hafizur Rehman IIEST, Shibpur
Prof. Himanshu Soni Nirma University, Ahmedabad
Dr. Harpreet Singh Jatana SCL, Chandigarh
Prof K S Dasgupta IIST, Thiruvantpuram
Navin Bisnoi Marvell Semiconductors
Prof. R N Patel Nirma University, Ahmedabad
Dr. Satya Gupta VLSI Society of India
Sudhir Naik eInfochips, Ahmedabad
Sumit Goswami Qualcomm
Prof. Vishwani Aggrawal Auburn University
   
General Co-Chair
Usha Mehta Nirma University, Ahmedabad
Sameer Chillarige Cadence
   
Technical Program Chair 
Prof. Ujjwal Guin Auburn University, USA
Technical Program Co-Chairs
Nikhil Sudhakaran Marvell, Bangalore
Prof Chester Rebeiro IIT Madras
   
Organizing Co-Chairs
Nilesh Ranpura eInfochips
Prof. Nagendra Gajjar Nirma University, Ahmedabad
   
Tutorial Co-Chairs
Supriyo Shrimani Synopsis Incorporation
Prof. R A Thakkar Gujarat University
   
PhD Forum Co-Chair
Prof. Indranil Sengupta IIT Kharagpur
Prof. Yogesh Trivedi Nirma University, Ahmedabad
   
Student Research Forum Chairs
Prof. Sivanantham VIT, Vellore,
Vishal Diwan Texas Instruments
   
Publication Co-Chairs
Prof. Anjali Diwan IEEE Gujarat Section
Prof. Vaishali Dhare Nirma University, Ahmedbad
   
Women-In-Engineering Co-Chairs
Prof. Manisha Shah IEEE Gujarat Section
Prof. Ruchi Gajjar Nirma University, Ahmedabad
   
Finance Chair
Prof. Sachin Gajjar Nirma University, Ahmedabad
Prof. Viranchi Pandya Nirma University, Ahmedabad
   
Local Organizing Chairs
Prof. Jayesh Patel Nirma University, Ahmedabad
Prof. Rutul Patel Nirma University, Ahmedabad
   
Registration Co-Chairs
Prof. Manisha Upadhyay Nirma University, Ahmedabad
Prof. Piyush Bhatasana Nirma University, Ahmedabad
   
Industry Forum Co-Chairs
Prachi Patel cadence, Ahmedabad
Nirav Nanavati eInfochips
Prof. Dhaval Shah Nirma University, Ahmedabad
   
Sponsorship Chairs
   
Prof. N M Devashrayee Nirma University, Ahmedabad
   
Web Chair
Prof. Akash Mecwan Nirma University, Ahmedabad
   
European Liaison
Prof. Ilia Polian University of Stuttgart, Germany
   
North America Liaison
Prof . Nagmeh Karimi University of Maryland, Baltimore County
   
Latin America Liaison
Prof Victor Hugo Champac  Instituto Nacional de Astrofisica, Mexico
Prof Tiago Balen UFRCG, Brazil
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Important Date
  • Conference Date

    Dec 17

    2024

    to

    Dec 20

    2024

  • Aug 15 2024

    Abstract Submission Deadline

  • Aug 15 2024

    Draft paper submission deadline

  • Oct 15 2024

    Draft Paper Acceptance Notification

  • Nov 15 2024

    Final Paper Deadline

Sponsored By
IEEE Computer Society
Supported By
VLSI Society of India
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