International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems—covering the complete cycle from design verification, design- fortest, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement. At ITC, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

ITC, the cornerstone of the Test Week event, offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including: formal paper sessions, tutorials, panel sessions, case studies, invited lectures, commercial exhibits and presentations, and a host of ancillary professional meetings.

Authors are invited to submit original, unpublished papers describing recent work in the field of test and design. In addition, authors are invited to submit high quality, practical, industry best practices. Submissions simultaneously under review or accepted by another conference, symposium or journal, will be summarily rejected.

Call for paper

Important date

Abstract submission deadline
Draft paper submission deadline
Draft paper acceptance notification
Final paper submission deadline

Submission Topics

  • 3D/2.5D Test

  • Adaptive Test in Practice

  • ATE/Probe Card Design

  • Advances in Boundary Scan

  • Bring-Up

  • Data-driven Methods

  • Data Exchange and Infrastructure

  • Defect-oriented Testing

  • DFM and Test

  • Diagnosis

  • Economics of Test

  • End-to-End Data Analysis

  • End-to-End System Security

  • Embedded BIST and DFT

  • Emerging Defect Mechanisms

  • Hardware Security and Trust

  • IoT Testing

  • Jitter, High-Speed I/O and RF Test

  • Known-Good-Die testing

  • Memory Test and Repair

  • MEMS Testing

  • Mixed-Signal and Analog Test

  • New Technologies and Test

  • On-Chip Test Compression

  • Online Test

  • Pre-Silicon Verification

  • Post- Silicon Validation

  • Power Issues in Test

  • Protocol-aware Test

  • Reliability and Resilience

  • Scan Based Test

  • SoC/SiP/NoC Test

  • Silicon Debug

  • Simulation and Emulation

  • System Test (Applications)

  • System Test (Hardware/Software)

  • Test-to-Design Feedback

  • Test Escape Analysis

  • Test Flow Optimizations

  • Test Generation and Validation

  • Test Resource Partitioning

  • Test Standards

  • Test Time Analysis and Reduction

  • Testing High Speed Optics/Photonics

  • Timing Test

  • Yield Analysis and Optimization

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Important Date
  • Conference Date

    Oct 30



    Nov 03


  • Feb 24 2018

    Abstract Submission Deadline

  • Mar 24 2018

    Draft paper submission deadline

  • Jun 05 2018

    Draft Paper Acceptance Notification

  • Jul 24 2018

    Final Paper Deadline

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Philadelphia Section
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